To facilitate the testing of a digital electronic device, such as an integrated circuit, or a circuit board containing a plurality of integrated circuits or even a group of boards, a testing technique known as Boundary-Scan has been developed. The Boundary-Scan test technique, which is now embodied in the ANSI/IEEE 1149.1 Standard on Boundary-Scan, is practiced by providing a Boundary-Scan cell, typically a single-bit shift register, at each output node (e.g., pin) of the electronic device which is coupled to an input node of another device. The Boundary-Scan cell is interposed between the output node and an internal logic block which drives the node, respectively. Each Boundary-Scan cell associated with each separate node is coupled in series with each of the other cells in a single chain (referred to as a Boundary-Scan chain) such that the output of each preceding cell is supplied to an input of the next succeeding cell in the chain.
Actual testing in accordance with the Boundary-Scan test technique is accomplished by shifting a known string of bits through the chain of Boundary-Scan cells so that each bit in the string is latched into a separate cell. For each Boundary-Scan cell coupled to an output node, the cell is "updated," i.e., the bit previously shifted into the cell now appears at the output node associated with the cell. As a consequence, a Boundary-Scan cell associated with an input node will "capture" (i.e., be supplied with) the bit appearing at an output node of another device which drives this input node. Thus, when each output node is "updated," the logic value presented to the Boundary Scan cell associated with the input node driven by the updated output node will likely change.
Once each Boundary-Scan cell associated with an input node has captured the bit appearing at the output node driving the input node, then the string of bits held by the chain of Boundary-Scan cells is shifted out. A comparison is then made between the string of shifted-out bits and a reference bit string representing the bits that would be obtained when the inter-device connections (i.e., the connections between the output and the input nodes of the devices) are fault-free. Any differences between the shifted-out bit string and the reference bit string are indicative of an error. For a more detailed description of the Boundary-Scan test technique embodied in the ANSI/IEEE Standard 1149.1, reference should be had to the publication IEEE Standard Test Access Port and Boundary-Scan Architecture, published by the Institute of Electrical and Electronics Engineers, New York, New York (1990), herein incorporated by reference.
As mentioned, when a Boundary-Scan cell is associated with an output node, the cell is interposed between the node and the internal logic of the device which drives the node. To allow either the Boundary-Scan cell or the internal logic of the device to separately drive the output node, a multiplexer is provided within the Boundary-Scan cell to multiplex signals from the cell and the internal logic of the device. Unfortunately, the multiplexer will impart a propagation delay to signals passing between the internal logic of the device and the corresponding output node during non-testing intervals. Such a propagation delay is undesirable, especially if the electronic device is to operate at high speeds. For this reason, high-speed electronic devices heretofore have not been provided with Boundary-Scan cells, thereby precluding the ability to test inter-device connections by the Boundary-Scan test technique described above.
Thus, there is a need for a Boundary-Scan cell which affords reduced propagation delays to enable such a Boundary-Scan cell to be employed in a high speed electronic device to facilitate Boundary-Scan testing.